The present invention relates, in general, to semiconductor devices, and more particularly, to a novel dielectric isolated semiconductor wafer that has a planar surface.
Previously, the semiconductor industry had utilized dielectric isolated wafers to implement dielectric isolated integrated circuits. The previous dielectric isolated wafers typically included a polysilicon substrate that had islands of single crystal silicon which were separated from the polysilicon substrate by a dielectric liner such as silicon dioxide. The dielectric liner isolated the single crystal silicon islands or tubs from the polysilicon substrate. The surface of each single crystal tub was covered with an epitaxial layer of single crystal silicon, and the surface of the polysilicon substrate was covered with an epitaxial layer of polysilicon.
One disadvantage of the previous dielectric isolated wafers was an interface trough that created a discontinuity in the dielectric isolated wafer's surface. The interface trough was a void in the epitaxial layer as it crossed the dielectric liner. Consequently, the interface trough separated the epitaxial layer covering the single crystal silicon tub from the epitaxial layer covering the polysilicon substrate. Because of the interface trough, it was difficult to create metal conductors on the dielectric isolated wafer's surface. Conductor patterns were generally formed by depositing a metal layer on the wafer and etching away unwanted sections of the metal. Metal that landed in the interface trough was difficult to remove and often remained in the trough after etching the metal layer. Metal conductors that crossed the interface trough often were shorted together by the metal residue in the interface trough. It was also difficult to deposit a metal layer that did not have a void as it traversed the interface trough. Consequently, metal conductors that were formed on previous dielectric isolated wafers generally had an open circuit that resulted from insufficient metal coverage of the interface trough, or a short created by metal residues in the interface trough.
In addition to causing opens and shorts in metal interconnect patterns, the dielectric isolation liner was exposed at the interface trough. Consequently, subsequent etching operations, employed during the formation of active and passive device elements in the tubs, etched the exposed dielectric and created a void in the dielectric between the single crystal silicon tub and the polysilicon substrate. This void weakened the mechanical bond between the single crystal silicon tub and the polysilicon substrate. Additionally, the void in the dielectric increased the size of the interface trough and further exacerbated the problems associated with metal interconnects.
Accordingly, it is desirable to have a dielectric isolated wafer that has a planar surface, that does not have an interface trough to cause opens and shorts in metal conductors, and that protects the dielectric liner from subsequent etching operations.